1. Field of the Invention
The present invention relates to input/output (I/O) buffers, and more particularly, to a supply and interface configurable input/output buffer.
2. Description of the Related Art
An input and/or output buffer is often used to make connections from the inside of an integrated circuit (IC) chip to devices that are external to the IC chip. Specifically, an output buffer is used to transfer signals that are generated internally in the IC chip to one of the IC chip's package pins so that the signal can be transferred to an external device. An input buffer is used to transfer a signal generated by an external device and received at one of the IC chip's package pins inside the IC chip to be used internally. A buffer which performs input and output through the same node, such as a single IC package pin, is referred to as an input/output (I/O) buffer, or simply, an I/O.
One example application of such I/Os is for connecting a DRAM controller with an external memory. In this application, the combination of high-speed, low overshoot/undershoot, and a stable noise margin are the target design specifications. In general, with respect to the output portion of an I/O, increasing the speed of the transition from low to high and high to low tends to have the disadvantage of increasing the overshoot and undershoot that is generated in a standard totem-pole output design. In I/Os that are designed to operate with two different voltage supply levels, such as for example 5 V and 3.3 V, another undesirable phenomenon occurs when the supply voltage is lowered from 5 V to 3.3 V. Specifically, the input buffer's TTL (transistor-transistor logic) trip point shifts down with the lower supply voltage on standard input structures, and the transition speed of the output buffer is degraded.
Thus, there is a need for an I/O architecture having high-speed, low overshoot/undershoot, and a stable, minimized noise margin that overcomes the disadvantages discussed above.